module mem_sram #(
    `include "tyrc_param.v")(
    input                     clk, 
    input                     rst_n,
    input                     write_en,
    input      [ADDR_WD -1:0] addr_in,
    input 	   [WORD_WD -1:0] data_in,
    output     [WORD_WD -1:0] data_out
);

reg [WORD_WD -1:0] mem[MEM_SIZE -1:0];
always @(posedge clk)begin
	if(write_en)begin
		mem[addr_in] <= data_in;
	end
end
assign data_out = mem[addr_in];

endmodule
